Sixty-seven Vietnamese trainees of a course under a training program jointly run by Vietnam’s National Innovation Center (NIC) and its Vietnamese and American partners have recently received their semiconductor engineering certificates.

The course was conducted in Hanoi as part of the chip design training cooperation between NIC and two American partners namely TreSemi and Cadence, along with Vietnamese collaborators, including tech giant FPT Corporation, Hanoi University of Science and Technology, Vietnam National University-Ho Chi Minh City, and the Da Nang City People’s Committee.

All the 67 chip design engineers have been highly appraised by American experts, said Dr. Vo Xuan Hoai, deputy director of NIC.

Among them, 20 have been recruited by chip design giants such as Synopsys, Faraday, Marvell, FPT, and others, while most of the rest have been granted scholarships for overseas training.

It is expected that each year, about 540 chip design engineers will be trained under this program.

Dr. Hoai affirmed that NIC and its partners can now train graduates from domestic universities in related fields, such as mechanics, electronics, and information technology, into semiconductor engineers or microchip designers after three-to-six-month training courses.

In addition to Tresemi and Cadence, NIC has actively coordinated with many other leading hi-tech firms such as U.S. giants Qorvo and Google, ARM of the UK, Siemens of Germany, and Samsung of South Korea, as well as with the Vietnam Innovation Network in Silicon Valley in the U.S., to open semiconductor training courses, said Minister of Planning and Investment Nguyen Chi Dung.

On Thursday, NIC will cooperate with Siemens to launch a semiconductor engineering training class, and at the same time announce a support program for universities through the use of Siemens' chip design software copyright.

The semiconductor human resource training plan, initiated and led by the Ministry of Planning and Investment, has received strong support and participation from various localities, enterprises, and universities, the minister said.

He commented that such active responses will help the plan’s goal of training 50,000 chip engineers, including 15,000 for the design stage, for the semiconductor industry by 2030 will be met soon.

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